Patents > Mark, Brian l.

R. Fan, A.T. Ishii, B.L. Mark, G. Ramamurthy, and Q. Ren, "An Optimal Buffer Management Scheme with Dynamic Queue Length Thresholds for ATM Switches," U.S. Patent No. 6,424,622, dated July 23, 2002.

 

R. Fan, B.L. Mark, and G. Ramamurthy, "Dynamic Rate Control Scheduler for ATM Networks," U.S. Patent No. 6,408,005, dated June 18, 2002.

 

R. Fan, B.L. Mark, G. Ramamurthy, and A.T. Ishii,"Time-Based Scheduler Architecture and Method for ATM Networks," U.S. Patent No. 6,389,019, dated May 14, 2002.

 

R. Fan, B.L. Mark, and G. Ramamurthy, "Large Capacity, Multiclass Core ATM Switch Architecture," U.S. Patent No. 6,324,165, dated Nov. 27, 2001.

B.L. Mark and G. Ramamurthy, "Real-time Estimation and Dynamic Renegotiation of UPC Values for Arbitrary Traffic Sources in ATM Networks," U.S. Patent No. 6,304,551, dated Oct. 16, 2001.

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